Features

 Solutions

• Smallest footprint, lowest power, high data

throughput bridging solutions for mobile applications

• Optimized footprint, logic density, IO count, IO

performance devices for IO management and

logic applications

• High IO/logic, lowest cost/IO, high IO devices for

IO expansion applications

 Flexible Architecture

• Logic Density ranging from 640 to 9.4K LUT4

• High IO to LUT ratio with up to 384 IO pins

 Advanced Packaging

• 0.4 mm pitch: 1K to 4K densities in very small

footprint WLCSP (2.5 mm x 2.5 mm to

3.8 mm x 3.8 mm) with 28 to 63 IOs

• 0.5 mm pitch: 640 to 9.4K LUT densities in

6 mm x 6 mm to 10 mm x 10 mm BGA packages

with up to 281 IOs

• 0.8 mm pitch: 1K to 9.4K densities with up to

384 IOs in BGA packages

 Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated gearing logic

• 7:1 Gearing for Display I/Os

• Generic DDR, DDRx2, DDRx4

 High Performance, Flexible I/O Buffer

• Programmable sysIOTM buffer supports wide

range of interfaces:

— LVCMOS 3.3/2.5/1.8/1.5/1.2

— LVTTL

— LVDS, Bus-LVDS, MLVDS, LVPECL

— MIPI D-PHY Emulated

— Schmitt trigger inputs, up to 0.5 V

hysteresis

• Ideal for IO bridging applications

• I/Os support hot socketing

• On-chip differential termination

• Programmable pull-up or pull-down mode